{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11500017","patent":{"patent_number":"US-11500017","title":"Testing memory elements using an internal testing interface","assignee":null,"inventors":[],"filing_date":"2021-03-29T00:00:00.000Z","publication_date":"2022-11-15T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G06F","G06F","G06F","G06F","G11C","G11C","G11C"],"num_claims":16,"abstract":"A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Testing memory elements using an internal testing interface","description":"A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals as","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11500017","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11500017","citation_suggestion":"Patentable. \"Testing memory elements using an internal testing interface\" (US-11500017). https://patentable.app/patents/US-11500017","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11500017","json":"https://patentable.app/api/llm-context/US-11500017","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:31:31.270Z"}