{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11500781","patent":{"patent_number":"US-11500781","title":"Methods and apparatuses for addressing memory caches","assignee":null,"inventors":[],"filing_date":"2020-11-30T00:00:00.000Z","publication_date":"2022-11-15T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G11C","G06F","G06F"],"num_claims":20,"abstract":"A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods and apparatuses for addressing memory caches","description":"A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are inde","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11500781","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11500781","citation_suggestion":"Patentable. \"Methods and apparatuses for addressing memory caches\" (US-11500781). https://patentable.app/patents/US-11500781","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11500781","json":"https://patentable.app/api/llm-context/US-11500781","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:25:01.853Z"}