{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11501131","patent":{"patent_number":"US-11501131","title":"Neural network hardware accelerator architectures and operating method thereof","assignee":null,"inventors":[],"filing_date":"2017-08-11T00:00:00.000Z","publication_date":"2022-11-15T00:00:00.000Z","cpc_codes":["G06N","G06F","G06F","G06N","G06N","G06N","G06N","G06N","G06N","G06N","G06N","G11C","G06F","G06N","G11C"],"num_claims":18,"abstract":"A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices containing instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row being connected to one of axons, outputs of the memory cells of a same column being connected to one of neurons; timestamp registers registering timestamps of the axons and the neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, wherein the processing unit updates the weight matrix in accordance with the adjusting values."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Neural network hardware accelerator architectures and operating method thereof","description":"A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices containin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11501131","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11501131","citation_suggestion":"Patentable. \"Neural network hardware accelerator architectures and operating method thereof\" (US-11501131). https://patentable.app/patents/US-11501131","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11501131","json":"https://patentable.app/api/llm-context/US-11501131","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:39:09.616Z"}