{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11501844","patent":{"patent_number":"US-11501844","title":"Memory device and test method thereof","assignee":null,"inventors":[],"filing_date":"2020-06-25T00:00:00.000Z","publication_date":"2022-11-15T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C"],"num_claims":16,"abstract":"A memory device adopting an on-chip ECC scheme includes a plurality of banks, each including a normal cell region and a parity cell region; a plurality of parity generation circuits, each generating parity bits for write data to be stored in the normal cell region within a corresponding bank; a test input circuit generating common test bits by comparing the parity bits of the respective banks, and generating individual test bits by comparing bits of the write data with the common test bits; a plurality of write circuits, each writing the write data to the normal cell region within the corresponding bank and writing the individual test bits to the parity cell region within the corresponding bank; and a plurality of test output circuits, each comparing data read from the normal region with the individual test bits read from the parity cell region within a corresponding bank."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device and test method thereof","description":"A memory device adopting an on-chip ECC scheme includes a plurality of banks, each including a normal cell region and a parity cell region; a plurality of parity generation circuits, each generating p","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11501844","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11501844","citation_suggestion":"Patentable. \"Memory device and test method thereof\" (US-11501844). https://patentable.app/patents/US-11501844","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11501844","json":"https://patentable.app/api/llm-context/US-11501844","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:05:26.590Z"}