{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11502126","patent":{"patent_number":"US-11502126","title":"Integrated circuit and fabrication method thereof","assignee":null,"inventors":[],"filing_date":"2020-11-13T00:00:00.000Z","publication_date":"2022-11-15T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integrated circuit and fabrication method thereof","description":"A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11502126","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11502126","citation_suggestion":"Patentable. \"Integrated circuit and fabrication method thereof\" (US-11502126). https://patentable.app/patents/US-11502126","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11502126","json":"https://patentable.app/api/llm-context/US-11502126","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:15:36.962Z"}