{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11502934","patent":{"patent_number":"US-11502934","title":"EZ-pass: an energy performance-efficient power-gating router architecture for scalable on-chip interconnect architecture","assignee":null,"inventors":[],"filing_date":"2019-08-21T00:00:00.000Z","publication_date":"2022-11-15T00:00:00.000Z","cpc_codes":["G06F","H04L","G06F","G06F","H04L","H04L","H04L","H04L","H04L","H04L"],"num_claims":25,"abstract":"With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-chip interconnect architecture consumes a significant portion of total parallel computing chip power. Power-gating is an effective technique to reduce power consumption by powering off the routers, but it suffers from a large wake-up latency to resume the full activity of routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. The present invention provides a new router architecture that remedies the large wake-up latency overheads while providing significant power savings. The invention takes advantage of a simple switch to transmit packets without waking up the router. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"EZ-pass: an energy performance-efficient power-gating router architecture for scalable on-chip interconnect architecture","description":"With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-ch","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11502934","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11502934","citation_suggestion":"Patentable. \"EZ-pass: an energy performance-efficient power-gating router architecture for scalable on-chip interconnect architecture\" (US-11502934). https://patentable.app/patents/US-11502934","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11502934","json":"https://patentable.app/api/llm-context/US-11502934","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:00:35.521Z"}