{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11507504","patent":{"patent_number":"US-11507504","title":"Memory sub-system for decoding non-power-of-two addressable unit address boundaries","assignee":null,"inventors":[],"filing_date":"2021-03-17T00:00:00.000Z","publication_date":"2022-11-22T00:00:00.000Z","cpc_codes":["G06F","G06F","H04B","H04B","H04B","H04W","H04W","H04W","G06F","G06F","H04B","H04L","H04L","H04W"],"num_claims":25,"abstract":"A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory sub-system for decoding non-power-of-two addressable unit address boundaries","description":"A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The sy","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11507504","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11507504","citation_suggestion":"Patentable. \"Memory sub-system for decoding non-power-of-two addressable unit address boundaries\" (US-11507504). https://patentable.app/patents/US-11507504","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11507504","json":"https://patentable.app/api/llm-context/US-11507504","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:16:42.700Z"}