{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11508426","patent":{"patent_number":"US-11508426","title":"Memory device, memory cell arrangement, and methods thereof","assignee":null,"inventors":[],"filing_date":"2021-10-26T00:00:00.000Z","publication_date":"2022-11-22T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Various aspects relate to a memory cell arrangement including: a field-effect transistor based capacitive memory cell including a memory element, wherein a memory state of the memory element defines a first memory state of the field-effect transistor based capacitive memory cell and wherein a second memory state of the memory element defines a second memory state of the field-effect transistor based capacitive memory cell; and a memory controller configured to, in the case that a charging state of the field-effect transistor based capacitive memory cell screens an actual threshold voltage state of the field-effect transistor based capacitive memory cell, cause a destructive read operation to determine whether the field-effect transistor based capacitive memory cell was, prior to the destructive read operation, residing in the first memory state or in the second memory state."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device, memory cell arrangement, and methods thereof","description":"Various aspects relate to a memory cell arrangement including: a field-effect transistor based capacitive memory cell including a memory element, wherein a memory state of the memory element defines a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11508426","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11508426","citation_suggestion":"Patentable. \"Memory device, memory cell arrangement, and methods thereof\" (US-11508426). https://patentable.app/patents/US-11508426","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11508426","json":"https://patentable.app/api/llm-context/US-11508426","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:48:08.845Z"}