{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11508649","patent":{"patent_number":"US-11508649","title":"Semiconductor package including substrate with outer insulating layer","assignee":null,"inventors":[],"filing_date":"2021-04-05T00:00:00.000Z","publication_date":"2022-11-22T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor package including substrate with outer insulating layer","description":"A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11508649","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11508649","citation_suggestion":"Patentable. \"Semiconductor package including substrate with outer insulating layer\" (US-11508649). https://patentable.app/patents/US-11508649","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11508649","json":"https://patentable.app/api/llm-context/US-11508649","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:36:03.115Z"}