{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11513948","patent":{"patent_number":"US-11513948","title":"Controller and memory system","assignee":null,"inventors":[],"filing_date":"2020-09-11T00:00:00.000Z","publication_date":"2022-11-29T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":14,"abstract":"A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Controller and memory system","description":"A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11513948","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11513948","citation_suggestion":"Patentable. \"Controller and memory system\" (US-11513948). https://patentable.app/patents/US-11513948","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11513948","json":"https://patentable.app/api/llm-context/US-11513948","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:04:31.428Z"}