{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11514973","patent":{"patent_number":"US-11514973","title":"Memory array with multiple power supply nodes and switch controllers for controlling power supply nodes for reliable write operation and method of operation","assignee":null,"inventors":[],"filing_date":"2020-08-26T00:00:00.000Z","publication_date":"2022-11-29T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory array with multiple power supply nodes and switch controllers for controlling power supply nodes for reliable write operation and method of operation","description":"A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interpos","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11514973","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11514973","citation_suggestion":"Patentable. \"Memory array with multiple power supply nodes and switch controllers for controlling power supply nodes for reliable write operation and method of operation\" (US-11514973). https://patentable.app/patents/US-11514973","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11514973","json":"https://patentable.app/api/llm-context/US-11514973","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:05:54.494Z"}