{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11515259","patent":{"patent_number":"US-11515259","title":"Method and device for the integration of semiconductor wafers","assignee":null,"inventors":[],"filing_date":"2018-10-17T00:00:00.000Z","publication_date":"2022-11-29T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":31,"abstract":"A method for the integration of semiconductor components in a confined space, in particular for 3D integration, in which, after positioning relative to a carrier substrate and/or a redistribution layer, the semiconductor components are protected and fixed in their relative position by introduction of a potting compound, characterized in that before the introduction of the potting compound, a glass substrate having a multiplicity of cutouts separated by partition walls and serving to receive a semiconductor component, is positioned in such a way that the semiconductor component is enclosed by the sidewall surfaces—facing it—of the respective partition walls of the glass substrate."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and device for the integration of semiconductor wafers","description":"A method for the integration of semiconductor components in a confined space, in particular for 3D integration, in which, after positioning relative to a carrier substrate and/or a redistribution laye","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11515259","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11515259","citation_suggestion":"Patentable. \"Method and device for the integration of semiconductor wafers\" (US-11515259). https://patentable.app/patents/US-11515259","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11515259","json":"https://patentable.app/api/llm-context/US-11515259","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:19:30.863Z"}