{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11515309","patent":{"patent_number":"US-11515309","title":"Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array","assignee":null,"inventors":[],"filing_date":"2020-12-17T00:00:00.000Z","publication_date":"2022-11-29T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":19,"abstract":"A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array","description":"A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11515309","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11515309","citation_suggestion":"Patentable. \"Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array\" (US-11515309). https://patentable.app/patents/US-11515309","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11515309","json":"https://patentable.app/api/llm-context/US-11515309","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:23:32.430Z"}