{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11520652","patent":{"patent_number":"US-11520652","title":"Memory device and operating method of the same","assignee":null,"inventors":[],"filing_date":"2020-09-18T00:00:00.000Z","publication_date":"2022-12-06T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G06F","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory device includes a memory cell array including memory cells connected to word lines and bit lines. Each of the memory cells includes a switch element and a memory element, and has a first state or a second state in which a threshold voltage is within a first voltage range or a second voltage range, lower than the first voltage range. A memory controller is configured to execute a first read operation for the memory cells using a first read voltage, higher than a median value of the first voltage range, program first defect memory cells turned off during the first read operation to the first state, execute a second read operation for the memory cells using a second read voltage, lower than a median value of the second voltage range, and execute a repair operation for second defect memory cells turned on during the second read operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device and operating method of the same","description":"A memory device includes a memory cell array including memory cells connected to word lines and bit lines. Each of the memory cells includes a switch element and a memory element, and has a first stat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11520652","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11520652","citation_suggestion":"Patentable. \"Memory device and operating method of the same\" (US-11520652). https://patentable.app/patents/US-11520652","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11520652","json":"https://patentable.app/api/llm-context/US-11520652","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T09:41:54.432Z"}