{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11521686","patent":{"patent_number":"US-11521686","title":"Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation","assignee":null,"inventors":[],"filing_date":"2021-03-31T00:00:00.000Z","publication_date":"2022-12-06T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation","description":"A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11521686","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11521686","citation_suggestion":"Patentable. \"Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation\" (US-11521686). https://patentable.app/patents/US-11521686","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11521686","json":"https://patentable.app/api/llm-context/US-11521686","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:16:26.686Z"}