{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11521896","patent":{"patent_number":"US-11521896","title":"Selective deposition of a protective layer to reduce interconnect structure critical dimensions","assignee":null,"inventors":[],"filing_date":"2020-09-04T00:00:00.000Z","publication_date":"2022-12-06T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Selective deposition of a protective layer to reduce interconnect structure critical dimensions","description":"In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11521896","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11521896","citation_suggestion":"Patentable. \"Selective deposition of a protective layer to reduce interconnect structure critical dimensions\" (US-11521896). https://patentable.app/patents/US-11521896","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11521896","json":"https://patentable.app/api/llm-context/US-11521896","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:38:40.051Z"}