{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11522062","patent":{"patent_number":"US-11522062","title":"Method of manufacturing an etch stop layer and an inter-layer dielectric on a source/drain region","assignee":null,"inventors":[],"filing_date":"2021-01-11T00:00:00.000Z","publication_date":"2022-12-06T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","B82Y"],"num_claims":20,"abstract":"In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of manufacturing an etch stop layer and an inter-layer dielectric on a source/drain region","description":"In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11522062","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11522062","citation_suggestion":"Patentable. \"Method of manufacturing an etch stop layer and an inter-layer dielectric on a source/drain region\" (US-11522062). https://patentable.app/patents/US-11522062","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11522062","json":"https://patentable.app/api/llm-context/US-11522062","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:08:27.530Z"}