{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11522678","patent":{"patent_number":"US-11522678","title":"Block cipher encryption for processor-accelerator memory mapped input/output communication","assignee":null,"inventors":[],"filing_date":"2021-06-08T00:00:00.000Z","publication_date":"2022-12-06T00:00:00.000Z","cpc_codes":["H04L","H04L","H04L","H04L"],"num_claims":20,"abstract":"Technologies for secure data transfer of MMIO data between a processor and an accelerator. A MIMO security engine includes a first block cipher pipeline to encrypt a count using a key; a first exclusive-OR (XOR) to generate a first XOR result of the encrypted count and a length multiplied by an authentication key; a second block cipher pipeline to encrypt (count+1) using the key; a second XOR to generate a second XOR result of plaintext data and the encrypted (count+1); a plurality of Galois field multipliers (GFMs) to perform Galois field multiplication on additional authenticated data (AAD), powers of the authentication key, and ciphertext data; and a plurality of exclusive-ORs (XORs) to combine results of the GFMs and the first XOR result to generate an authentication tag. Other embodiments are described and claimed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Block cipher encryption for processor-accelerator memory mapped input/output communication","description":"Technologies for secure data transfer of MMIO data between a processor and an accelerator. A MIMO security engine includes a first block cipher pipeline to encrypt a count using a key; a first exclusi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11522678","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11522678","citation_suggestion":"Patentable. \"Block cipher encryption for processor-accelerator memory mapped input/output communication\" (US-11522678). https://patentable.app/patents/US-11522678","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11522678","json":"https://patentable.app/api/llm-context/US-11522678","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:20:24.475Z"}