{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11526448","patent":{"patent_number":"US-11526448","title":"Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning","assignee":null,"inventors":[],"filing_date":"2019-09-27T00:00:00.000Z","publication_date":"2022-12-13T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning","description":"An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11526448","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11526448","citation_suggestion":"Patentable. \"Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning\" (US-11526448). https://patentable.app/patents/US-11526448","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11526448","json":"https://patentable.app/api/llm-context/US-11526448","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:45:29.526Z"}