{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11527460","patent":{"patent_number":"US-11527460","title":"Device topologies for high current lateral power semiconductor devices","assignee":null,"inventors":[],"filing_date":"2020-10-30T00:00:00.000Z","publication_date":"2022-12-13T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":26,"abstract":"A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Device topologies for high current lateral power semiconductor devices","description":"A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance.","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11527460","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11527460","citation_suggestion":"Patentable. \"Device topologies for high current lateral power semiconductor devices\" (US-11527460). https://patentable.app/patents/US-11527460","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11527460","json":"https://patentable.app/api/llm-context/US-11527460","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:32:58.132Z"}