{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11528037","patent":{"patent_number":"US-11528037","title":"Hardware architecture for local erasure correction in SSD/UFS via maximally recoverable codes","assignee":null,"inventors":[],"filing_date":"2021-06-17T00:00:00.000Z","publication_date":"2022-12-13T00:00:00.000Z","cpc_codes":["G06N"],"num_claims":20,"abstract":"A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix H1 of columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix H2 of columns of H located on non-erased coordinates of code C; a neural network that calculates matrix J1 that is an approximate inverse of matrix H1. The matrix J1 is used to determine new erasures in the parity matrix H and new erased coordinates. Matrices H1 and H2 are updated, and the updated H1 is provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J1, matrix H2, and a non-erased part of codeword C."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Hardware architecture for local erasure correction in SSD/UFS via maximally recoverable codes","description":"A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs mat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11528037","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11528037","citation_suggestion":"Patentable. \"Hardware architecture for local erasure correction in SSD/UFS via maximally recoverable codes\" (US-11528037). https://patentable.app/patents/US-11528037","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11528037","json":"https://patentable.app/api/llm-context/US-11528037","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:04:55.069Z"}