{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11531630","patent":{"patent_number":"US-11531630","title":"Memory controller, memory system and operating method of the memory system for scheduling data access across channels of memory chips within the memory system","assignee":null,"inventors":[],"filing_date":"2020-10-23T00:00:00.000Z","publication_date":"2022-12-20T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory controller, memory system and operating method of the memory system for scheduling data access across channels of memory chips within the memory system","description":"An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11531630","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11531630","citation_suggestion":"Patentable. \"Memory controller, memory system and operating method of the memory system for scheduling data access across channels of memory chips within the memory system\" (US-11531630). https://patentable.app/patents/US-11531630","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11531630","json":"https://patentable.app/api/llm-context/US-11531630","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T10:00:07.298Z"}