{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11532338","patent":{"patent_number":"US-11532338","title":"Mediating between asynchronous clock domains while preventing false indications of FIFO occupancy","assignee":null,"inventors":[],"filing_date":"2021-04-06T00:00:00.000Z","publication_date":"2022-12-20T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C"],"num_claims":26,"abstract":"An electronic circuit includes a memory buffer and control logic. The memory buffer is configured to transfer data from a first domain to a second domain of the circuit, the first and the second domains operate in synchronization with respective clock signals. The control logic is configured to maintain a write indicator in the first domain indicative of a next write position in the memory buffer for storing data, to maintain a read indicator in the second domain indicative of a next read position in the memory buffer for retrieving the stored data, to generate in the second domain, based on the write and the read indicators, a first signal that is indicative of whether the memory buffer has data for reading or has become empty, and retain the first signal in a state that indicates that the memory buffer has become empty, until writing to the memory buffer resumes."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Mediating between asynchronous clock domains while preventing false indications of FIFO occupancy","description":"An electronic circuit includes a memory buffer and control logic. The memory buffer is configured to transfer data from a first domain to a second domain of the circuit, the first and the second domai","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11532338","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11532338","citation_suggestion":"Patentable. \"Mediating between asynchronous clock domains while preventing false indications of FIFO occupancy\" (US-11532338). https://patentable.app/patents/US-11532338","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11532338","json":"https://patentable.app/api/llm-context/US-11532338","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:19:42.251Z"}