{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11532344","patent":{"patent_number":"US-11532344","title":"Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell","assignee":null,"inventors":[],"filing_date":"2021-11-18T00:00:00.000Z","publication_date":"2022-12-20T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell","description":"A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11532344","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11532344","citation_suggestion":"Patentable. \"Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell\" (US-11532344). https://patentable.app/patents/US-11532344","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11532344","json":"https://patentable.app/api/llm-context/US-11532344","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:16:00.368Z"}