{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11533054","patent":{"patent_number":"US-11533054","title":"Ternary logic circuit device","assignee":null,"inventors":[],"filing_date":"2021-09-29T00:00:00.000Z","publication_date":"2022-12-20T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":7,"abstract":"A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Ternary logic circuit device","description":"A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11533054","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11533054","citation_suggestion":"Patentable. \"Ternary logic circuit device\" (US-11533054). https://patentable.app/patents/US-11533054","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11533054","json":"https://patentable.app/api/llm-context/US-11533054","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T12:26:13.938Z"}