{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11940918","patent":{"patent_number":"US-11940918","title":"Memory pipeline control in a hierarchical memory system","assignee":null,"inventors":[],"filing_date":"2023-02-13T00:00:00.000Z","publication_date":"2024-03-26T00:00:00.000Z","cpc_codes":["A61B","G06F","G06F","G06F","G06F","G06F","G06F","A61B","A61B","A61B","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory pipeline control in a hierarchical memory system","description":"In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a hi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11940918","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11940918","citation_suggestion":"Patentable. \"Memory pipeline control in a hierarchical memory system\" (US-11940918). https://patentable.app/patents/US-11940918","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11940918","json":"https://patentable.app/api/llm-context/US-11940918","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T14:37:12.464Z"}