{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11942145","patent":{"patent_number":"US-11942145","title":"Static random access memory layout","assignee":null,"inventors":[],"filing_date":"2022-05-06T00:00:00.000Z","publication_date":"2024-03-26T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":20,"abstract":"The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Static random access memory layout","description":"The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply rou","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11942145","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11942145","citation_suggestion":"Patentable. \"Static random access memory layout\" (US-11942145). https://patentable.app/patents/US-11942145","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11942145","json":"https://patentable.app/api/llm-context/US-11942145","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:30:47.559Z"}