{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11942165","patent":{"patent_number":"US-11942165","title":"Architecture and method for NAND memory programming","assignee":null,"inventors":[],"filing_date":"2022-04-20T00:00:00.000Z","publication_date":"2024-03-26T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Architecture and method for NAND memory programming","description":"A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11942165","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11942165","citation_suggestion":"Patentable. \"Architecture and method for NAND memory programming\" (US-11942165). https://patentable.app/patents/US-11942165","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11942165","json":"https://patentable.app/api/llm-context/US-11942165","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:15:35.491Z"}