{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11942331","patent":{"patent_number":"US-11942331","title":"Method for preparing semiconductor device structure with isolation patterns having different heights","assignee":null,"inventors":[],"filing_date":"2021-12-14T00:00:00.000Z","publication_date":"2024-03-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":14,"abstract":"A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer; performing a first energy treating process to form a plurality of first treated portions in the energy-sensitive layer; performing a second energy treating process to form a plurality of second treated portions in the energy-sensitive layer; removing the first treated portions and the second treated portions to respectively form a plurality of first openings and a plurality of second openings; transferring the first openings and the second openings into the target layer to respectively form a plurality of third openings and a plurality of fourth openings; and transferring the third openings and the fourth openings into the semiconductor substrate to respectively form a plurality of fifth openings and a plurality of sixth openings."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for preparing semiconductor device structure with isolation patterns having different heights","description":"A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer;","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11942331","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11942331","citation_suggestion":"Patentable. \"Method for preparing semiconductor device structure with isolation patterns having different heights\" (US-11942331). https://patentable.app/patents/US-11942331","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11942331","json":"https://patentable.app/api/llm-context/US-11942331","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T14:01:54.856Z"}