{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11942372","patent":{"patent_number":"US-11942372","title":"Dielectric protection layer in middle-of-line interconnect structure manufacturing method","assignee":null,"inventors":[],"filing_date":"2021-08-27T00:00:00.000Z","publication_date":"2024-03-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Dielectric protection layer in middle-of-line interconnect structure manufacturing method","description":"In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11942372","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11942372","citation_suggestion":"Patentable. \"Dielectric protection layer in middle-of-line interconnect structure manufacturing method\" (US-11942372). https://patentable.app/patents/US-11942372","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11942372","json":"https://patentable.app/api/llm-context/US-11942372","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:10:58.573Z"}