{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11943332","patent":{"patent_number":"US-11943332","title":"Low depth AES SBox architecture for area-constraint hardware","assignee":null,"inventors":[],"filing_date":"2020-03-06T00:00:00.000Z","publication_date":"2024-03-26T00:00:00.000Z","cpc_codes":["H04L","H04L"],"num_claims":11,"abstract":"A substitution box, SBox, circuit that performs an SBox computational step when comprised in cryptographic circuitry. The SBox circuit comprises: a first circuit part comprising digital circuitry that generates a 4-bit first output signal (Y) from an 8-bit input signal (U); a second circuit part, configured to operate in parallel with the first circuit part and to generate a 32-bit second output signal (L) from the 8-bit input signal (U), wherein the 32-bit second output signal (L) consists of four 8-bit sub-results; and a third circuit part configured to produce four preliminary 8-bit results (K) by scalar multiplying each of the four 8-bit sub-results by a respective one bit of the 4-bit first output signal (Y), and to produce an 8-bit output signal (R) by summing the four preliminary 8-bit results (K). The first circuit part is configured to generate the 4-bit first output signal (Y) from the input signal (U) by performing a calculation that comprises a first linear matrix operation, a Galois Field (GF) multiplication, and a GF inversion; and the second circuit part is configured to generate the second output signal (L) from the input signal (U) by performing a calculation that comprises a second linear matrix operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Low depth AES SBox architecture for area-constraint hardware","description":"A substitution box, SBox, circuit that performs an SBox computational step when comprised in cryptographic circuitry. The SBox circuit comprises: a first circuit part comprising digital circuitry that","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11943332","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11943332","citation_suggestion":"Patentable. \"Low depth AES SBox architecture for area-constraint hardware\" (US-11943332). https://patentable.app/patents/US-11943332","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11943332","json":"https://patentable.app/api/llm-context/US-11943332","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:48:19.103Z"}