{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11947454","patent":{"patent_number":"US-11947454","title":"Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system","assignee":null,"inventors":[],"filing_date":"2022-06-07T00:00:00.000Z","publication_date":"2024-04-02T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available. The sub-NUMA bit mask and the client allocation bit mask can be combined to create a cache allocation vector that a cache allocation request to allocate a line serviced by one of processing cores."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system","description":"Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11947454","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11947454","citation_suggestion":"Patentable. \"Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system\" (US-11947454). https://patentable.app/patents/US-11947454","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11947454","json":"https://patentable.app/api/llm-context/US-11947454","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:15:20.005Z"}