{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11948624","patent":{"patent_number":"US-11948624","title":"Memory bit cell array including contention-free column reset circuit, and related methods","assignee":null,"inventors":[],"filing_date":"2021-12-23T00:00:00.000Z","publication_date":"2024-04-02T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":17,"abstract":"A column in a memory array includes one bit cell circuit in each row for storing information about the row. The bit cell circuits store data in a data node and a complement data node in a cross-coupled inverter circuit. Toggling the nodes in a cross-coupled inverter includes discharging a charged node in contention with a charge current provided in the cross-coupled inverter circuit. The column circuit includes a first voltage supply circuit to decouple the cross-coupled inverter circuits from a first voltage rail to cut off charging current in response to a column set signal in a column set operation. The cross-coupled inverters of the bit cell circuits in the column circuit are coupled to a first voltage supply line. The column set input controls the first voltage supply circuit to decouple the first voltage supply line from a first voltage rail."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory bit cell array including contention-free column reset circuit, and related methods","description":"A column in a memory array includes one bit cell circuit in each row for storing information about the row. The bit cell circuits store data in a data node and a complement data node in a cross-couple","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11948624","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11948624","citation_suggestion":"Patentable. \"Memory bit cell array including contention-free column reset circuit, and related methods\" (US-11948624). https://patentable.app/patents/US-11948624","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11948624","json":"https://patentable.app/api/llm-context/US-11948624","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:44:58.691Z"}