{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11948649","patent":{"patent_number":"US-11948649","title":"Anti-fuse memory cell and data read-write circuit thereof","assignee":null,"inventors":[],"filing_date":"2021-10-15T00:00:00.000Z","publication_date":"2024-04-02T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":8,"abstract":"An anti-fuse memory cell and a data read-write circuit thereof. The anti-fuse memory cell comprises a base, the base is provided with an N-well and a non-N-well region; the non-N-well region is provided with a first NMOS transistor; a gate of the first NMOS transistor is used for inputting a first selection signal; the N-well is provided with a PMOS transistor and a varactor; a gate of the PMOS transistor and a gate of the varactor are both connected to a drain of the first NMOS transistor; and a drain, a source and a substrate of the PMOS transistor and a drain, a source, and a substrate of the varactor are all connected to a controllable power supply."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Anti-fuse memory cell and data read-write circuit thereof","description":"An anti-fuse memory cell and a data read-write circuit thereof. The anti-fuse memory cell comprises a base, the base is provided with an N-well and a non-N-well region; the non-N-well region is provid","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11948649","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11948649","citation_suggestion":"Patentable. \"Anti-fuse memory cell and data read-write circuit thereof\" (US-11948649). https://patentable.app/patents/US-11948649","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11948649","json":"https://patentable.app/api/llm-context/US-11948649","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T08:36:53.168Z"}