{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11948801","patent":{"patent_number":"US-11948801","title":"Method and system for etch depth control in III-V semiconductor devices","assignee":null,"inventors":[],"filing_date":"2021-06-23T00:00:00.000Z","publication_date":"2024-04-02T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":18,"abstract":"A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for etch depth control in III-V semiconductor devices","description":"A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11948801","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11948801","citation_suggestion":"Patentable. \"Method and system for etch depth control in III-V semiconductor devices\" (US-11948801). https://patentable.app/patents/US-11948801","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11948801","json":"https://patentable.app/api/llm-context/US-11948801","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T14:46:48.726Z"}