{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11950402","patent":{"patent_number":"US-11950402","title":"Memory device having 2-transistor vertical memory cell and shield structures","assignee":null,"inventors":[],"filing_date":"2023-04-21T00:00:00.000Z","publication_date":"2024-04-02T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":20,"abstract":"Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device having 2-transistor vertical memory cell and shield structures","description":"Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11950402","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11950402","citation_suggestion":"Patentable. \"Memory device having 2-transistor vertical memory cell and shield structures\" (US-11950402). https://patentable.app/patents/US-11950402","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11950402","json":"https://patentable.app/api/llm-context/US-11950402","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T11:53:56.545Z"}