{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11950407","patent":{"patent_number":"US-11950407","title":"Memory architecture with shared bitline at back-end-of-line","assignee":null,"inventors":[],"filing_date":"2020-03-24T00:00:00.000Z","publication_date":"2024-04-02T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":23,"abstract":"Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory architecture with shared bitline at back-end-of-line","description":"Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11950407","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11950407","citation_suggestion":"Patentable. \"Memory architecture with shared bitline at back-end-of-line\" (US-11950407). https://patentable.app/patents/US-11950407","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11950407","json":"https://patentable.app/api/llm-context/US-11950407","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:50:40.546Z"}