{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11953969","patent":{"patent_number":"US-11953969","title":"Compute through power loss hardware approach for processing device having nonvolatile logic memory","assignee":null,"inventors":[],"filing_date":"2021-08-17T00:00:00.000Z","publication_date":"2024-04-09T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Compute through power loss hardware approach for processing device having nonvolatile logic memory","description":"A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11953969","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11953969","citation_suggestion":"Patentable. \"Compute through power loss hardware approach for processing device having nonvolatile logic memory\" (US-11953969). https://patentable.app/patents/US-11953969","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11953969","json":"https://patentable.app/api/llm-context/US-11953969","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T17:59:16.402Z"}