{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11955167","patent":{"patent_number":"US-11955167","title":"Computing-in-memory accelerator design with dynamic analog RAM cell and associated low power techniques with sparsity management","assignee":null,"inventors":[],"filing_date":"2022-01-12T00:00:00.000Z","publication_date":"2024-04-09T00:00:00.000Z","cpc_codes":["G11C","G11C","G06F","G06N","G06N","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":13,"abstract":"Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a read bitline; a switch transistor M2 in electrical communication with the read-access transistor M1; a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Computing-in-memory accelerator design with dynamic analog RAM cell and associated low power techniques with sparsity management","description":"Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a rea","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11955167","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11955167","citation_suggestion":"Patentable. \"Computing-in-memory accelerator design with dynamic analog RAM cell and associated low power techniques with sparsity management\" (US-11955167). https://patentable.app/patents/US-11955167","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11955167","json":"https://patentable.app/api/llm-context/US-11955167","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:32:25.465Z"}