{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11955991","patent":{"patent_number":"US-11955991","title":"Apparatuses and methods for pipelining memory operations with error correction coding","assignee":null,"inventors":[],"filing_date":"2022-04-18T00:00:00.000Z","publication_date":"2024-04-09T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":11,"abstract":"Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatuses and methods for pipelining memory operations with error correction coding","description":"Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11955991","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11955991","citation_suggestion":"Patentable. \"Apparatuses and methods for pipelining memory operations with error correction coding\" (US-11955991). https://patentable.app/patents/US-11955991","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11955991","json":"https://patentable.app/api/llm-context/US-11955991","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T02:39:54.831Z"}