{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11961740","patent":{"patent_number":"US-11961740","title":"Manufacturing method for integrating gate dielectric layers of different thicknesses","assignee":null,"inventors":[],"filing_date":"2021-11-01T00:00:00.000Z","publication_date":"2024-04-16T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":15,"abstract":"The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Manufacturing method for integrating gate dielectric layers of different thicknesses","description":"The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickn","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11961740","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11961740","citation_suggestion":"Patentable. \"Manufacturing method for integrating gate dielectric layers of different thicknesses\" (US-11961740). https://patentable.app/patents/US-11961740","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11961740","json":"https://patentable.app/api/llm-context/US-11961740","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:10:37.004Z"}