{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11961878","patent":{"patent_number":"US-11961878","title":"Interconnect layout for semiconductor device","assignee":null,"inventors":[],"filing_date":"2021-12-13T00:00:00.000Z","publication_date":"2024-04-16T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Interconnect layout for semiconductor device","description":"A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interco","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11961878","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11961878","citation_suggestion":"Patentable. \"Interconnect layout for semiconductor device\" (US-11961878). https://patentable.app/patents/US-11961878","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11961878","json":"https://patentable.app/api/llm-context/US-11961878","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:51:02.561Z"}