{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11962327","patent":{"patent_number":"US-11962327","title":"Iterative decoding technique for correcting DRAM device failures","assignee":null,"inventors":[],"filing_date":"2022-08-26T00:00:00.000Z","publication_date":"2024-04-16T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":21,"abstract":"Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Iterative decoding technique for correcting DRAM device failures","description":"Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC)","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11962327","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11962327","citation_suggestion":"Patentable. \"Iterative decoding technique for correcting DRAM device failures\" (US-11962327). https://patentable.app/patents/US-11962327","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11962327","json":"https://patentable.app/api/llm-context/US-11962327","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:16:44.281Z"}