{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11968828","patent":{"patent_number":"US-11968828","title":"Method of forming a semiconductor device with a dual gate dielectric layer having middle portion thinner than the edge portions","assignee":null,"inventors":[],"filing_date":"2019-07-09T00:00:00.000Z","publication_date":"2024-04-23T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of forming a semiconductor device with a dual gate dielectric layer having middle portion thinner than the edge portions","description":"A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11968828","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11968828","citation_suggestion":"Patentable. \"Method of forming a semiconductor device with a dual gate dielectric layer having middle portion thinner than the edge portions\" (US-11968828). https://patentable.app/patents/US-11968828","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11968828","json":"https://patentable.app/api/llm-context/US-11968828","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T18:36:30.166Z"}