{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11971821","patent":{"patent_number":"US-11971821","title":"Computing system with write-back and invalidation in a hierarchical cache structure based on at least one designated key identification code","assignee":null,"inventors":[],"filing_date":"2022-10-14T00:00:00.000Z","publication_date":"2024-04-30T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":36,"abstract":"A computing system with a first instruction of an instruction set architecture (ISA) for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for write-back and invalidation in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one write-back and invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each write-back and invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Computing system with write-back and invalidation in a hierarchical cache structure based on at least one designated key identification code","description":"A computing system with a first instruction of an instruction set architecture (ISA) for write-back and invalidation in a hierarchical cache structure based on one single designated key identification","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11971821","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11971821","citation_suggestion":"Patentable. \"Computing system with write-back and invalidation in a hierarchical cache structure based on at least one designated key identification code\" (US-11971821). https://patentable.app/patents/US-11971821","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11971821","json":"https://patentable.app/api/llm-context/US-11971821","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:20:23.859Z"}