{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11972188","patent":{"patent_number":"US-11972188","title":"Rail power density aware standard cell placement for integrated circuits","assignee":null,"inventors":[],"filing_date":"2021-10-19T00:00:00.000Z","publication_date":"2024-04-30T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":28,"abstract":"To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Rail power density aware standard cell placement for integrated circuits","description":"To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to b","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11972188","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11972188","citation_suggestion":"Patentable. \"Rail power density aware standard cell placement for integrated circuits\" (US-11972188). https://patentable.app/patents/US-11972188","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11972188","json":"https://patentable.app/api/llm-context/US-11972188","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T12:47:32.325Z"}