{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11972806","patent":{"patent_number":"US-11972806","title":"Read techniques to reduce read errors in a memory device","assignee":null,"inventors":[],"filing_date":"2022-06-10T00:00:00.000Z","publication_date":"2024-04-30T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Read techniques to reduce read errors in a memory device","description":"The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11972806","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11972806","citation_suggestion":"Patentable. \"Read techniques to reduce read errors in a memory device\" (US-11972806). https://patentable.app/patents/US-11972806","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11972806","json":"https://patentable.app/api/llm-context/US-11972806","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:15:42.250Z"}