{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11972820","patent":{"patent_number":"US-11972820","title":"Non-volatile memory with tier-wise ramp down after program-verify","assignee":null,"inventors":[],"filing_date":"2022-08-30T00:00:00.000Z","publication_date":"2024-04-30T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Non-volatile memory with tier-wise ramp down after program-verify","description":"Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by appl","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11972820","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11972820","citation_suggestion":"Patentable. \"Non-volatile memory with tier-wise ramp down after program-verify\" (US-11972820). https://patentable.app/patents/US-11972820","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11972820","json":"https://patentable.app/api/llm-context/US-11972820","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:21:51.485Z"}