{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11973080","patent":{"patent_number":"US-11973080","title":"Embedded semiconductor region for latch-up susceptibility improvement","assignee":null,"inventors":[],"filing_date":"2022-07-18T00:00:00.000Z","publication_date":"2024-04-30T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Embedded semiconductor region for latch-up susceptibility improvement","description":"The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type subst","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11973080","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11973080","citation_suggestion":"Patentable. \"Embedded semiconductor region for latch-up susceptibility improvement\" (US-11973080). https://patentable.app/patents/US-11973080","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11973080","json":"https://patentable.app/api/llm-context/US-11973080","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:44:07.946Z"}