{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11973130","patent":{"patent_number":"US-11973130","title":"Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized MOSFET and SONOS co-integration","assignee":null,"inventors":[],"filing_date":"2021-01-27T00:00:00.000Z","publication_date":"2024-04-30T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":28,"abstract":"A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the first, second and third regions, wherein at least part of the ONO stack is protected from the etching by the first TEOS layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized MOSFET and SONOS co-integration","description":"A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first t","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11973130","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11973130","citation_suggestion":"Patentable. \"Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized MOSFET and SONOS co-integration\" (US-11973130). https://patentable.app/patents/US-11973130","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11973130","json":"https://patentable.app/api/llm-context/US-11973130","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T14:42:34.977Z"}